High speed, general purpose data processing systems have been designed in the prior art to handle certain generic types of data processing problems. In particular, data processing systems designed to handle a variety of matrix manipulation problems, called array processors, have become exceedingly important in signal analysis where signals are characterized by means of digital filtering and fast fourier transform analysis. A specific example of such a prior art system is shown in U.S. Pat. No. 4,041,461 by Gary L. Kratz, et al, assigned to the instant assignee, which discloses a signal analyzer system which employs a control processor for centrally controlling the operation of an arithmetic processor and a storage transfer controller by means of sending a sequence of command instructions and control parameters to these respective, dependent processor elements.
In the prior art multiprocessing system represented by the Kratz, et al patent, the control processor was required to continually issue specific command words to the arithmetic processor and the storage transfer controller and a typical problem solution would require that seventy percent of the control processor's time be devoted to the preparation of commands dealing with trivial functions to be carried out by the arithmetic processor or storage transfer controller. In addition, when mutually dependent functions were to be performed by the arithmetic processor and storage transfer controller had to load a working store prior to the execution of the arithmetic process by the arithmetic processor and then the arithmetic processor had to indicate to the storage transfer controller when to unload the results of that arithmetic process, it was necessary to communicate these completion status points between these dependent processors through the control processor itself. These communication interrupts consume still more of the time of the control processor. Thus, less than twenty percent of the control processor's time was available for system executive functions as a resource allocator and task manager for the system. This resulted in impeding the total throughput of the system and rendering it incapable of expansion to control additional dependent processors.